Low power high speed bypassing based multipliers with modified adders for dsp applications
نویسندگان
چکیده
Braun multiplier is one of the parallel array multipliers, which is used for unsigned numbers multiplication. This paper presents different techniques for optimizing the multiplier in power and delay parameters. The dynamic power of a multiplier can be reduced by using bypassing techniques and delay can be reduced by replacing ripple carry adder in the last stage of full adders by optimized adders in different logics, Double pass transistor logic (DPL) and Transmission Gate (TG). Different logic style adders are designed and implemented in 0.13um CMOS technology and its functional parameters are compared and the best result is incorporated in the column bypassed Braun multiplier. And the new multiplier is used to implement a MAC unit which is more efficient.
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